Speed Optimization and Capacitor Mismatch Calibration for High-Resolution High-Speed Pipelined A/D Converters

System-on-a-chip (SOC) requires integration of analog circuits and digital circuits on a single silicon chip to decrease cost, power dissipation, volume and radiant noise from the data bus on the printed circuit board (PCB). For these mixed-signal intergrated circuits, the standard digital CMOS technology is the best choice in view of cost, power dissipation and implementation convenience. The analog-to-digital converter (ADC) is an important building block as a bridge of the analog world to the digital section in SOC. Wide applications of digital signal processing (DSP) techniques into different fields, such as high-resolution image and video processing systems, asynchronous digital subscriber loop (ASDL), wireless communations and so on, require urgently high-speed, high-resolution, embeddable ADCs with low voltage, low power dissipation, small area and easy integration in the standard CMOS technology. Since 1970s, a large variety of architectures have been proposed one after another Time-Interleaved ADC, and so forth. Oversampling delta-sigma ADC [1-3] can obtain high resolution through oversample and noise-shaping techniques. However, its conversion speed is generally less than 1MHz. Flash ADC [4-8] is the fastest architecture, presently, because of its fully parallel processing feature. However, fully parallel processing produces a disadvantage that power dissipation and chip area increase exponentially with resolution and therefore, it is not suitable for high-resolution ADCs. Folding and Interpolating ADC[9-12] employes folding and interpolating techniques to eliminate Flash ADC's drawback that ciruit scale increases exponentially with resolution. However, folding processing restricts input signals' bandwith, and high requirements for the transistor match make it insuitable for CMOS implementations. Subranging ADC [13-15] decreases circuit scale and power dissipation through dividing conversion range and converting input signals step by step. However, its multi-step serial conversion greatly degrades conversion speed. 3 Pipelined ADC [16-20] introduces sample-and-hold circuits into subranging architecture to hold analog residues from previous stages. This feature allows pipeline stages convert analog signals in parallel and therefore, greatly improves conversion ratio. Parallel time-interleaved ADC [21-23] utilizes time-interleaved technique to obtain higher speed than Flash ADC. However, non-uniform sample together with mismatch of the channels' offset and gain makes it difficult to obtain higher resolution. Generally, for ADCs with high resolution of no-less-than 10 bit, high speed of more-than 1MS/s and easy integration for system, CMOS pipelined architecture is the reasonable scheme. Pipelined ADC employs subranging conversion and pipeline operation, implements high-resolution analog-to-digital conversion and meanwhile, maintains high speed and low power dissipation. Furthermore, Pipelined structure by itself …